mips.h File Reference

Define human readable registers, coprocessor 0 registers, cause and status register masks, memory segment addresses, context record offsets, and cache functions and register offsets. More...

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Defines

#define zero   $0

Human readable register names.

#define AT   $1

asm temp - uppercase because of ".set at"

#define v0   $2

return value

#define a0   $4

argument 0 to 3

#define t0   $8

caller saved 0 to 7

#define s0   $16

callee saved 0 to 7

#define t8   $24

caller saved 8 and 9

#define jp   $25

PIC jump register.

#define k0   $26

kernel scratch

#define gp   $28

global pointer

#define s8   $28

callee saved 8, alternative to gp

#define sp   $29

stack pointer

#define fp   $30

frame pointer

#define s9   $30

callee saved 9, alternative to fp

#define ra   $31

return address

#define CP0_INDEX   $0

Coprocessor 0 registers.

#define CP0_RANDOM   $1

Random pointer into TLB.

#define CP0_ENTRYLO0   $2

Even page TLB entry.

#define CP0_ENTRYLO1   $3

Odd page TLB entry.

#define CP0_CONTEXT   $4

Hold PTE base and VPN on TLB exception.

#define CP0_PGMASK   $5

Mask for virtual address on TLB matching.

#define CP0_WIRED   $6

Boundary between random and wired entries.

#define CP0_BADVADDR   $8

Bad address generated by TLB exceptions.

#define CP0_COUNT   $9

Timer counter.

#define CP0_ENTRYHI   $10

Hi half of TLB (VPN+ASID).

#define CP0_COMPARE   $11

interrupt when CP0_COUNT == CP0_COMPARE

#define CP0_STATUS   $12

Various run time processor information.

#define CP0_CAUSE   $13

Identifies cause of interrupt/exception.

#define CP0_EPC   $14

Return address after exception handling.

#define CP0_PRID   $15

processor identification

#define CP0_CONFIG   $16

configuration register (select 0, 1)

#define CP0_DIAG   $22

implementation dependent (diagnostic?)

#define PRID_REV   0x000000FF

Processor ID masks.

#define PRID_CPUID   0x0000FF00

CPU ID.

#define PRID_REV_WRT54G   0x29

Platform specific values and macros.

#define CAUSE_EXC   0x0000007C

Cause register interrupt masks.

#define CAUSE_IRQ   0x0000FF00

interrupt request bits

#define CAUSE_EXC_SHIFT   2

exception code shift value

#define CAUSE_IRQ_SHIFT   8

interrupt request shift value

#define CAUSE_SW0   0x00000100

software interrupt

#define CAUSE_HW0   0x00000400

eth0 interrupt

#define CAUSE_HW1   0x00000800

serial interrupt

#define CAUSE_HW5   0x00008000

timer interrupt

#define STATUS_IE   0x00000001

Status register masks.

#define STATUS_EXL   0x00000002

Exception Level.

#define STATUS_ERL   0x00000004

Error Level.

#define STATUS_SW0   CAUSE_SW0

Software interrupt enable.

#define STATUS_HW0   CAUSE_HW0

Hardware interrupt enable.

#define STATUS_HW1   CAUSE_HW1

UART interrupt enable.

#define STATUS_HW5   CAUSE_HW5

Timer interrupt enable.

#define KUSEG_BASE   0x00000000

Define kernel memory segments for MIPS32 processors.

#define KUSEG_SIZE   0x80000000

userspace mapped (2 GB)

#define KSEG0_BASE   0x80000000

kernel unmapped, cached base

#define KSEG0_SIZE   0x20000000

kernel unmapped, cahced (512 MB)

#define KSEG1_BASE   0xA0000000

kernel unmapped, uncached base

#define KSEG1_SIZE   0x20000000

kernel unmapped, uncached (512 MB)

#define KSEG2_BASE   0xC0000000

kernel mapped base

#define KSEG2_SIZE   0x40000000

kernel mapped (1 GB)

#define CONTEXT   64

Context record offsets.

#define RA_CON   (CONTEXT - 8)

return address

#define S9_CON   52

callee saved registers

#define CONFIG1_IS   22

Cache register locations within the Config1 register.

#define CONFIG1_DS   13

data cache

#define CONFIG1_MASK   7

value mask

#define INDEX_STORE_TAG_I   0x8

Cache functions.

#define FILL_I_CACHE   0x14

fill instruction cache

#define INDEX_STORE_TAG_D   0x9

invalidate data cache tag

Detailed Description

Define human readable registers, coprocessor 0 registers, cause and status register masks, memory segment addresses, context record offsets, and cache functions and register offsets.

Id: mips.h 1447 2008-08-12 19:23:34Z mschul

Definition in file mips.h.

Define Documentation

#define CAUSE_EXC 0x0000007C

Cause register interrupt masks.

exception code bits

Definition at line 100 of file mips.h.

Referenced by exception().

#define CONFIG1_IS 22

Cache register locations within the Config1 register.

instruction cache

Definition at line 162 of file mips.h.

#define CONTEXT 64

Context record offsets.

context record size in bytes context record size in words

Definition at line 143 of file mips.h.

#define CP0_INDEX $0

Coprocessor 0 registers.

Index pointer into TLB

Definition at line 61 of file mips.h.

#define INDEX_STORE_TAG_I 0x8

Cache functions.

invalidate instruction cache tag

Definition at line 173 of file mips.h.

#define KUSEG_BASE 0x00000000

Define kernel memory segments for MIPS32 processors.

userspace mapped base

Definition at line 131 of file mips.h.

#define PRID_REV 0x000000FF

Processor ID masks.

Revision

Definition at line 85 of file mips.h.

Referenced by platforminit().

#define STATUS_IE 0x00000001

Status register masks.

Global interrupt enable

Definition at line 116 of file mips.h.

ent intdispatch CP0_CAUSE addiu CAUSE_EXC and k1 beq lui k0 lw k1 nop beq nop jr k0 IRQREC_SIZE sw CP0_CAUSE mfc0 CP0_EPC sw CP0_STATUS sw sp li CAUSE_EXC and a2 beq zero $0

Human readable register names.

wired zero

Definition at line 22 of file mips.h.


Defines
#define	zero $0
	Human readable register names.
#define	AT $1
	asm temp - uppercase because of ".set at"
#define	v0 $2
	return value
#define	a0 $4
	argument 0 to 3
#define	t0 $8
	caller saved 0 to 7
#define	s0 $16
	callee saved 0 to 7
#define	t8 $24
	caller saved 8 and 9
#define	jp $25
	PIC jump register.
#define	k0 $26
	kernel scratch
#define	gp $28
	global pointer
#define	s8 $28
	callee saved 8, alternative to gp
#define	sp $29
	stack pointer
#define	fp $30
	frame pointer
#define	s9 $30
	callee saved 9, alternative to fp
#define	ra $31
	return address
#define	CP0_INDEX $0
	Coprocessor 0 registers.
#define	CP0_RANDOM $1
	Random pointer into TLB.
#define	CP0_ENTRYLO0 $2
	Even page TLB entry.
#define	CP0_ENTRYLO1 $3
	Odd page TLB entry.
#define	CP0_CONTEXT $4
	Hold PTE base and VPN on TLB exception.
#define	CP0_PGMASK $5
	Mask for virtual address on TLB matching.
#define	CP0_WIRED $6
	Boundary between random and wired entries.
#define	CP0_BADVADDR $8
	Bad address generated by TLB exceptions.
#define	CP0_COUNT $9
	Timer counter.
#define	CP0_ENTRYHI $10
	Hi half of TLB (VPN+ASID).
#define	CP0_COMPARE $11
	interrupt when CP0_COUNT == CP0_COMPARE
#define	CP0_STATUS $12
	Various run time processor information.
#define	CP0_CAUSE $13
	Identifies cause of interrupt/exception.
#define	CP0_EPC $14
	Return address after exception handling.
#define	CP0_PRID $15
	processor identification
#define	CP0_CONFIG $16
	configuration register (select 0, 1)
#define	CP0_DIAG $22
	implementation dependent (diagnostic?)
#define	PRID_REV 0x000000FF
	Processor ID masks.
#define	PRID_CPUID 0x0000FF00
	CPU ID.
#define	PRID_REV_WRT54G 0x29
	Platform specific values and macros.
#define	CAUSE_EXC 0x0000007C
	Cause register interrupt masks.
#define	CAUSE_IRQ 0x0000FF00
	interrupt request bits
#define	CAUSE_EXC_SHIFT 2
	exception code shift value
#define	CAUSE_IRQ_SHIFT 8
	interrupt request shift value
#define	CAUSE_SW0 0x00000100
	software interrupt
#define	CAUSE_HW0 0x00000400
	eth0 interrupt
#define	CAUSE_HW1 0x00000800
	serial interrupt
#define	CAUSE_HW5 0x00008000
	timer interrupt
#define	STATUS_IE 0x00000001
	Status register masks.
#define	STATUS_EXL 0x00000002
	Exception Level.
#define	STATUS_ERL 0x00000004
	Error Level.
#define	STATUS_SW0 CAUSE_SW0
	Software interrupt enable.
#define	STATUS_HW0 CAUSE_HW0
	Hardware interrupt enable.
#define	STATUS_HW1 CAUSE_HW1
	UART interrupt enable.
#define	STATUS_HW5 CAUSE_HW5
	Timer interrupt enable.
#define	KUSEG_BASE 0x00000000
	Define kernel memory segments for MIPS32 processors.
#define	KUSEG_SIZE 0x80000000
	userspace mapped (2 GB)
#define	KSEG0_BASE 0x80000000
	kernel unmapped, cached base
#define	KSEG0_SIZE 0x20000000
	kernel unmapped, cahced (512 MB)
#define	KSEG1_BASE 0xA0000000
	kernel unmapped, uncached base
#define	KSEG1_SIZE 0x20000000
	kernel unmapped, uncached (512 MB)
#define	KSEG2_BASE 0xC0000000
	kernel mapped base
#define	KSEG2_SIZE 0x40000000
	kernel mapped (1 GB)
#define	CONTEXT 64
	Context record offsets.
#define	RA_CON (CONTEXT - 8)
	return address
#define	S9_CON 52
	callee saved registers
#define	CONFIG1_IS 22
	Cache register locations within the Config1 register.
#define	CONFIG1_DS 13
	data cache
#define	CONFIG1_MASK 7
	value mask
#define	INDEX_STORE_TAG_I 0x8
	Cache functions.
#define	FILL_I_CACHE 0x14
	fill instruction cache
#define	INDEX_STORE_TAG_D 0x9
	invalidate data cache tag